ELC + ABS

The ARM's big.LITTLE technology implements a smart idea of combining high-performance cores are with low power ones to deliver peak-performance capacity at a lower average power cost. However, as big.LITTLE effectively is an asymmetrical MP, mainline SMP-oriented kernel "fair" scheduler can't take advantage of it. This talk will show what should be changed in the mainline scheduler to fit big.LITTLE architecture.

Multiple attempts were carried out to come up with the improvements implementing these changes, with the most notable coming from Codeaurora and Linaro/ARM. This talk will explain these implementations specifying their differences and similarities, and provide power and performance comparisons for both.